433 lines
32 KiB
C
433 lines
32 KiB
C
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/*!
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\file gd32f10x_exmc.h
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\brief definitions for the EXMC
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\version 2014-12-26, V1.0.0, firmware for GD32F10x
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\version 2017-06-20, V2.0.0, firmware for GD32F10x
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\version 2018-07-31, V2.1.0, firmware for GD32F10x
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F10X_EXMC_H
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#define GD32F10X_EXMC_H
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#include "gd32f10x.h"
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/* EXMC definitions */
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#define EXMC (EXMC_BASE) /*!< EXMC register base address */
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/* registers definitions */
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/* NOR/PSRAM */
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#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */
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#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */
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#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */
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#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register 1 */
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#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register 1 */
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#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register 1 */
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#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register 2 */
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#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register 2 */
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#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register 2 */
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#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register 3 */
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#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register 3 */
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#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register 3 */
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/* NAND/PC card */
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#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register 1 */
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#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register 1 */
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#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register 1 */
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#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register 1 */
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#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register 1 */
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#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register 2 */
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#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register 2 */
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#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register 2 */
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#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register 2 */
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#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register 2 */
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#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register 3 */
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#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register 3 */
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#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register 3 */
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#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register 3 */
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#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */
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/* bits definitions */
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/* NOR/PSRAM */
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/* EXMC_SNCTLx,x=0..3 */
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#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
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#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */
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#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
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#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
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#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
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#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */
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#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
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#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */
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#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
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#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
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#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
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#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
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#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */
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#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */
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/* EXMC_SNTCFGx,x=0..3 */
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#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */
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#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */
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#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */
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#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
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#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
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#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */
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#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */
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/* EXMC_SNWTCFGx,x=0..3 */
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#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */
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#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */
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#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */
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#define EXMC_SNWTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
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#define EXMC_SNWTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */
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#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */
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/* NAND/PC card */
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/* EXMC_NPCTLx,x=1..3 */
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#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */
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#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */
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#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */
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#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */
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#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */
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#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */
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#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */
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#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */
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/* EXMC_NPINTENx,x=1..3 */
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#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */
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#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */
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#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */
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#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */
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#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */
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#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */
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#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */
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/* EXMC_NPCTCFGx,x=1..3 */
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#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */
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#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */
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#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */
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#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */
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/* EXMC_NPATCFGx,x=1..3 */
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#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */
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#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */
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#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */
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#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */
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/* EXMC_PIOTCFG3 */
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#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */
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#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */
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#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */
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#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */
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/* EXMC_NECCx,x=1,2 */
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#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */
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/* constants definitions */
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/* EXMC NOR/SRAM timing initialize struct */
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typedef struct
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{
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uint32_t asyn_access_mode; /*!< asynchronous access mode */
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uint32_t syn_data_latency; /*!< configure the data latency */
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uint32_t syn_clk_division; /*!< configure the clock divide ratio */
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uint32_t bus_latency; /*!< configure the bus latency */
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uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
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uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
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uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
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}exmc_norsram_timing_parameter_struct;
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/* EXMC NOR/SRAM initialize struct */
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typedef struct
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{
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uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
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uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
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uint32_t extended_mode; /*!< enable or disable the extended mode */
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uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
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uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */
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uint32_t memory_write; /*!< enable or disable the write operation */
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uint32_t nwait_config; /*!< NWAIT signal configuration */
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uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */
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uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
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uint32_t burst_mode; /*!< enable or disable the burst mode */
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uint32_t databus_width; /*!< specifies the databus width of external memory */
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uint32_t memory_type; /*!< specifies the type of external memory */
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uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
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exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing
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parameters for read if the extended mode is used */
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exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */
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}exmc_norsram_parameter_struct;
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/* EXMC NAND/PC card timing initialize struct */
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typedef struct
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{
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uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
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uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
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uint32_t waittime; /*!< configure the minimum wait time */
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uint32_t setuptime; /*!< configure the address setup time */
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}exmc_nand_pccard_timing_parameter_struct;
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/* EXMC NAND initialize struct */
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typedef struct
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{
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uint32_t nand_bank; /*!< select the bank of NAND */
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uint32_t ecc_size; /*!< the page size for the ECC calculation */
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uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
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uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
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uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */
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uint32_t databus_width; /*!< the NAND flash databus width */
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uint32_t wait_feature; /*!< enables or disables the wait feature */
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exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
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exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
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}exmc_nand_parameter_struct;
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/* EXMC PC card initialize struct */
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typedef struct
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{
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uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
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uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
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uint32_t wait_feature; /*!< enables or disables the Wait feature */
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exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
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exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
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exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */
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}exmc_pccard_parameter_struct;;
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/* EXMC register address */
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#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */
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#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */
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#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration register */
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#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control register */
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#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable register */
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#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration register */
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#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */
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#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC register */
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/* NOR bank memory data bus width */
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#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
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#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */
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#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */
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/* NOR bank memory type */
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#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
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#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
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#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
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#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
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/* asynchronous access mode */
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#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
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#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */
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#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */
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#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */
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#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */
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/* data latency for NOR flash */
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#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
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#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */
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#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */
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#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */
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#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */
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#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */
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#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */
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#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */
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#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */
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#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */
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#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */
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#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */
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#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */
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#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */
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#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */
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#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */
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#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */
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/* synchronous clock divide ratio */
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#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
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#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */
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#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */
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#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */
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/* ECC size */
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#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
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#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */
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#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */
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#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */
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#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */
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#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */
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#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */
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/* ALE to RE delay */
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#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
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#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */
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#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */
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#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */
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#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */
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#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */
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#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */
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#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */
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#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */
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#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */
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#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */
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#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */
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#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */
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#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */
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#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */
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#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */
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#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */
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/* CLE to RE delay */
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#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
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#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */
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#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */
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#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */
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#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */
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#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */
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#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */
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#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */
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#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */
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#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */
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#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */
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#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */
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#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */
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#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */
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#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */
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#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */
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#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */
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/* NAND bank memory data bus width */
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#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
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#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */
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#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */
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/* EXMC NOR/SRAM bank region definition */
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#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
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#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */
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#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */
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#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */
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/* EXMC NOR/SRAM write mode */
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#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */
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#define EXMC_SYN_WRITE ((uint32_t)0x00080000U) /*!< synchronous write mode */
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/* EXMC NWAIT signal configuration */
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#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */
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#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */
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/* EXMC NWAIT signal polarity configuration */
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#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
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#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */
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/* EXMC NAND/PC card bank definition */
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#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */
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#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */
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#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */
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/* EXMC flag bits */
|
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#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */
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#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */
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#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */
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#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */
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/* EXMC interrupt flag bits */
|
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|
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#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */
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#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */
|
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#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */
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/* function declarations */
|
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/* deinitialize EXMC NOR/SRAM region */
|
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void exmc_norsram_deinit(uint32_t norsram_region);
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/* exmc_norsram_parameter_struct parameter initialize */
|
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void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
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/* initialize EXMC NOR/SRAM region */
|
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void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
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/* EXMC NOR/SRAM bank enable */
|
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void exmc_norsram_enable(uint32_t norsram_region);
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/* EXMC NOR/SRAM bank disable */
|
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void exmc_norsram_disable(uint32_t norsram_region);
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/* deinitialize EXMC NAND bank */
|
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void exmc_nand_deinit(uint32_t nand_bank);
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/* initialize EXMC NAND bank */
|
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void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
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/* exmc_nand_init_struct parameter initialize */
|
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void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
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/* EXMC NAND bank enable */
|
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|
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void exmc_nand_enable(uint32_t nand_bank);
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/* EXMC NAND bank disable */
|
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|
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void exmc_nand_disable(uint32_t nand_bank);
|
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|
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/* enable or disable the EXMC NAND ECC function */
|
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|
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void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue);
|
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/* get the EXMC ECC value */
|
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uint32_t exmc_ecc_get(uint32_t nand_bank);
|
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|
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/* deinitialize EXMC PC card bank */
|
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|
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void exmc_pccard_deinit(void);
|
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/* initialize EXMC PC card bank */
|
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void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
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/* exmc_pccard_parameter_struct parameter initialize */
|
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|
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void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
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|
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/* EXMC PC card bank enable */
|
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|
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void exmc_pccard_enable(void);
|
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|
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/* EXMC PC card bank disable */
|
||
|
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void exmc_pccard_disable(void);
|
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|
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/* enable EXMC interrupt */
|
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|
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void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source);
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|
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/* disable EXMC interrupt */
|
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|
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void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source);
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/* check EXMC flag is set or not */
|
||
|
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FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag);
|
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|
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/* clear EXMC flag */
|
||
|
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void exmc_flag_clear(uint32_t bank, uint32_t flag);
|
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|
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/* check EXMC flag is set or not */
|
||
|
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FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source);
|
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/* clear EXMC flag */
|
||
|
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void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source);
|
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#endif /* GD32F10X_EXMC_H */
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