431 lines
29 KiB
C
431 lines
29 KiB
C
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/*!
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\file gd32f10x_sdio.h
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\brief definitions for the SDIO
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\version 2014-12-26, V1.0.0, firmware for GD32F10x
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\version 2017-06-20, V2.0.0, firmware for GD32F10x
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\version 2018-07-31, V2.1.0, firmware for GD32F10x
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F10X_SDIO_H
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#define GD32F10X_SDIO_H
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#include "gd32f10x.h"
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/* SDIO definitions */
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#define SDIO SDIO_BASE
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/* registers definitions */
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#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */
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#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */
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#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */
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#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */
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#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */
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#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */
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#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */
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#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */
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#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */
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#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */
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#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */
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#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */
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#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */
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#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */
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#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */
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#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */
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#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */
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#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */
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/* bits definitions */
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/* SDIO_PWRCTL */
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#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */
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/* SDIO_CLKCTL */
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#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */
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#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */
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#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */
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#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */
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#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */
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#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */
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#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */
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/* SDIO_CMDAGMT */
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#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */
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/* SDIO_CMDCTL */
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#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */
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#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */
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#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */
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#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */
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#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */
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#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */
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#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */
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#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */
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#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */
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/* SDIO_DATATO */
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#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */
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/* SDIO_DATALEN */
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#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */
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/* SDIO_DATACTL */
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#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */
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#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */
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#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */
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#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */
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#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */
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#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */
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#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */
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#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */
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#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */
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/* SDIO_STAT */
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#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */
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#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */
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#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */
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#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */
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#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */
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#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */
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#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */
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#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */
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#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */
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#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */
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#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */
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#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */
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#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */
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#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */
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#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */
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#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */
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#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */
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#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */
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#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */
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#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */
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#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */
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#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */
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#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */
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#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */
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/* SDIO_INTC */
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#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */
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#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */
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#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */
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#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */
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#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */
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#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */
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#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */
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#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */
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#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */
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#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */
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#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */
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#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */
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#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */
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/* SDIO_INTEN */
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#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */
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#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */
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#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */
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#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */
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#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */
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#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */
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#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */
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#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */
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#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */
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#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */
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#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */
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#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */
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#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */
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#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */
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#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */
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#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */
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#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */
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#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */
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#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */
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#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */
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#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */
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#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */
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#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */
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#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */
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/* SDIO_FIFO */
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#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */
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/* constants definitions */
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/* SDIO flags */
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#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */
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#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */
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#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */
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#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */
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#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */
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#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */
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#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */
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#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */
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#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */
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#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */
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#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */
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#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */
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#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */
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#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */
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#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */
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#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */
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#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */
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#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */
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#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */
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#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */
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#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */
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#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */
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#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */
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#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */
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/* SDIO interrupt enable or disable */
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#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */
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#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */
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#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */
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#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */
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#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */
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#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */
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#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */
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#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */
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#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */
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#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */
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#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */
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#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */
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#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */
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#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */
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#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */
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#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */
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#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */
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#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */
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#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */
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#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */
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#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */
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#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */
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#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */
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#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */
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/* SDIO interrupt flags */
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#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */
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#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */
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#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */
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#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */
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#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt */
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#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt */
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#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */
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#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */
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#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt */
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#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt */
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#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */
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#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */
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#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */
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#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */
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#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt */
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#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt */
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#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt */
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#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt */
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#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt */
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#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt */
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#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */
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#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */
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#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */
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#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */
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/* SDIO power control */
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#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
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#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */
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#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */
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/* SDIO card bus mode control */
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#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
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#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */
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#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */
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#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */
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/* SDIO_CLK clock edge selection */
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#define SDIO_SDIOCLKEDGE_RISING ((uint32_t)0x00000000U)/*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */
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#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */
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/* clock bypass enable or disable */
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#define SDIO_CLOCKBYPASS_DISABLE ((uint32_t)0x00000000U)/*!< no bypass */
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#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */
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/* SDIO_CLK clock dynamic switch on/off for power saving */
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#define SDIO_CLOCKPWRSAVE_DISABLE ((uint32_t)0x00000000U)/*!< SDIO_CLK clock is always on */
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#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */
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/* SDIO command response type */
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#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
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#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */
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#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */
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#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */
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/* command state machine wait type */
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#define SDIO_WAITTYPE_NO ((uint32_t)0x00000000U)/*!< not wait interrupt */
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#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */
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#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */
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#define SDIO_RESPONSE0 ((uint32_t)0x00000000U)/*!< card response[31:0]/card response[127:96] */
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#define SDIO_RESPONSE1 ((uint32_t)0x00000001U)/*!< card response[95:64] */
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#define SDIO_RESPONSE2 ((uint32_t)0x00000002U)/*!< card response[63:32] */
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#define SDIO_RESPONSE3 ((uint32_t)0x00000003U)/*!< card response[31:1], plus bit 0 */
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/* SDIO data block size */
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#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
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#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */
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#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */
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#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */
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#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */
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#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */
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#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */
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#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */
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#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */
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#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */
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#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */
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#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */
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#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */
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#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */
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#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */
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#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */
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/* SDIO data transfer mode */
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#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000U)/*!< block transfer */
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#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */
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/* SDIO data transfer direction */
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#define SDIO_TRANSDIRECTION_TOCARD ((uint32_t)0x00000000U)/*!< write data to card */
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#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */
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/* SDIO read wait type */
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#define SDIO_READWAITTYPE_DAT2 ((uint32_t)0x00000000U)/*!< read wait control using SDIO_DAT[2] */
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#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */
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/* function declarations */
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/* deinitialize the SDIO */
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void sdio_deinit(void);
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/* configure the SDIO clock */
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void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division);
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/* enable hardware clock control */
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void sdio_hardware_clock_enable(void);
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/* disable hardware clock control */
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void sdio_hardware_clock_disable(void);
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/* set different SDIO card bus mode */
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void sdio_bus_mode_set(uint32_t bus_mode);
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/* set the SDIO power state */
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void sdio_power_state_set(uint32_t power_state);
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/* get the SDIO power state */
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uint32_t sdio_power_state_get(void);
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/* enable SDIO_CLK clock output */
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void sdio_clock_enable(void);
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/* disable SDIO_CLK clock output */
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void sdio_clock_disable(void);
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/* configure the command index, argument, response type, wait type and CSM to send command */
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/* configure the command and response */
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void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type);
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/* set the command state machine wait type */
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void sdio_wait_type_set(uint32_t wait_type);
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/* enable the CSM(command state machine) */
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void sdio_csm_enable(void);
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/* disable the CSM(command state machine) */
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void sdio_csm_disable(void);
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/* get the last response command index */
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uint8_t sdio_command_index_get(void);
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/* get the response for the last received command */
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uint32_t sdio_response_get(uint32_t responsex);
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/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */
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/* configure the data timeout, data length and data block size */
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void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize);
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/* configure the data transfer mode and direction */
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void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction);
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/* enable the DSM(data state machine) for data transfer */
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void sdio_dsm_enable(void);
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/* disable the DSM(data state machine) */
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void sdio_dsm_disable(void);
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/* write data(one word) to the transmit FIFO */
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void sdio_data_write(uint32_t data);
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/* read data(one word) from the receive FIFO */
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uint32_t sdio_data_read(void);
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/* get the number of remaining data bytes to be transferred to card */
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uint32_t sdio_data_counter_get(void);
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/* get the number of words remaining to be written or read from FIFO */
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uint32_t sdio_fifo_counter_get(void);
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/* enable the DMA request for SDIO */
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void sdio_dma_enable(void);
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/* disable the DMA request for SDIO */
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void sdio_dma_disable(void);
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/* get the flags state of SDIO */
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FlagStatus sdio_flag_get(uint32_t flag);
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/* clear the pending flags of SDIO */
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void sdio_flag_clear(uint32_t flag);
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/* enable the SDIO interrupt */
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void sdio_interrupt_enable(uint32_t int_flag);
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/* disable the SDIO interrupt */
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void sdio_interrupt_disable(uint32_t int_flag);
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/* get the interrupt flags state of SDIO */
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FlagStatus sdio_interrupt_flag_get(uint32_t int_flag);
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/* clear the interrupt pending flags of SDIO */
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void sdio_interrupt_flag_clear(uint32_t int_flag);
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/* enable the read wait mode(SD I/O only) */
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void sdio_readwait_enable(void);
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/* disable the read wait mode(SD I/O only) */
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void sdio_readwait_disable(void);
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/* enable the function that stop the read wait process(SD I/O only) */
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void sdio_stop_readwait_enable(void);
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/* disable the function that stop the read wait process(SD I/O only) */
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void sdio_stop_readwait_disable(void);
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/* set the read wait type(SD I/O only) */
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void sdio_readwait_type_set(uint32_t readwait_type);
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/* enable the SD I/O mode specific operation(SD I/O only) */
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void sdio_operation_enable(void);
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/* disable the SD I/O mode specific operation(SD I/O only) */
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void sdio_operation_disable(void);
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/* enable the SD I/O suspend operation(SD I/O only) */
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void sdio_suspend_enable(void);
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/* disable the SD I/O suspend operation(SD I/O only) */
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void sdio_suspend_disable(void);
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/* enable the CE-ATA command(CE-ATA only) */
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void sdio_ceata_command_enable(void);
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/* disable the CE-ATA command(CE-ATA only) */
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void sdio_ceata_command_disable(void);
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/* enable the CE-ATA interrupt(CE-ATA only) */
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void sdio_ceata_interrupt_enable(void);
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/* disable the CE-ATA interrupt(CE-ATA only) */
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void sdio_ceata_interrupt_disable(void);
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/* enable the CE-ATA command completion signal(CE-ATA only) */
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void sdio_ceata_command_completion_enable(void);
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/* disable the CE-ATA command completion signal(CE-ATA only) */
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void sdio_ceata_command_completion_disable(void);
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#endif /* GD32F10X_SDIO_H */
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