186 lines
9.3 KiB
C
186 lines
9.3 KiB
C
/*
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* Copyright (C) 2016 Rockchip Electronics Co., Ltd.
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* Authors:
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* Zhiqin Wei <wzq@rock-chips.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _RGA_DRIVER_H_
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#define _RGA_DRIVER_H_
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#ifndef ENABLE
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#define ENABLE 1
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#endif
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#ifndef DISABLE
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#define DISABLE 0
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#endif
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX,
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* RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */
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typedef enum _Rga_SURF_FORMAT {
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RK_FORMAT_RGBA_8888 = 0x0 << 8, /* [0:31] R:G:B:A 8:8:8:8 little endian */
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RK_FORMAT_RGBX_8888 = 0x1 << 8, /* [0:31] R:G:B:X 8:8:8:8 little endian */
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RK_FORMAT_RGB_888 = 0x2 << 8, /* [0:23] R:G:B 8:8:8 little endian */
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RK_FORMAT_BGRA_8888 = 0x3 << 8, /* [0:31] B:G:R:A 8:8:8:8 little endian */
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RK_FORMAT_RGB_565 = 0x4 << 8, /* [0:15] R:G:B 5:6:5 little endian */
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RK_FORMAT_RGBA_5551 = 0x5 << 8, /* [0:15] R:G:B:A 5:5:5:1 little endian */
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RK_FORMAT_RGBA_4444 = 0x6 << 8, /* [0:15] R:G:B:A 4:4:4:4 little endian */
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RK_FORMAT_BGR_888 = 0x7 << 8, /* [0:23] B:G:R 8:8:8 little endian */
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RK_FORMAT_YCbCr_422_SP = 0x8 << 8, /* 2 plane YCbCr little endian
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* plane 0: [0:7] Y
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* plane 1: 2x1 subsampled [0:15] Cb:Cr 8:8 */
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RK_FORMAT_YCbCr_422_P = 0x9 << 8, /* 3 plane YCbCr little endian
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* plane 0: [0:7] Y
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* plane 1: 2x1 subsampled [0:7] Cb
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* plane 2: 2x1 subsampled [0:7] Cr */
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RK_FORMAT_YCbCr_420_SP = 0xa << 8, /* 2 plane YCbCr little endian
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* plane 0: [0:7] Y
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* plane 1: 2x2 subsampled [0:15] Cr:Cb 8:8 */
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RK_FORMAT_YCbCr_420_P = 0xb << 8, /* 3 plane YCbCr little endian
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* plane 0: [0:7] Y
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* plane 1: 2x2 subsampled [0:7] Cb
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* plane 2: 2x2 subsampled [0:7] Cr */
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RK_FORMAT_YCrCb_422_SP = 0xc << 8, /* 2 plane YCbCr little endian
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* plane 0: [0:7] Y
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* plane 1: 2x1 subsampled [0:15] Cb:Cr 8:8 */
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RK_FORMAT_YCrCb_422_P = 0xd << 8, /* 3 plane YCbCr little endian
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* plane 0: [0:7] Y
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* plane 1: 2x1 subsampled [0:7] Cr
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* plane 2: 2x1 subsampled [0:7] Cb */
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RK_FORMAT_YCrCb_420_SP = 0xe << 8, /* 2 plane YCbCr little endian
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* plane 0: [0:7] Y
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* plane 1: 2x2 subsampled [0:15] Cb:Cr 8:8 */
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RK_FORMAT_YCrCb_420_P = 0xf << 8, /* 3 plane YCbCr little endian
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* plane 0: [0:7] Y
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* plane 1: 2x2 subsampled [0:7] Cr
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* plane 2: 2x2 subsampled [0:7] Cb */
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RK_FORMAT_BPP1 = 0x10 << 8, /* [0] little endian */
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RK_FORMAT_BPP2 = 0x11 << 8, /* [0:1] little endian */
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RK_FORMAT_BPP4 = 0x12 << 8, /* [0:3] little endian */
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RK_FORMAT_BPP8 = 0x13 << 8, /* [0:7] little endian */
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RK_FORMAT_Y4 = 0x14 << 8, /* [0:3] Y little endian */
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RK_FORMAT_YCbCr_400 = 0x15 << 8, /* [0:7] Y little endian */
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RK_FORMAT_BGRX_8888 = 0x16 << 8, /* [0:31] B:G:R:X 8:8:8:8 little endian */
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RK_FORMAT_YVYU_422 = 0x18 << 8, /* [0:31] Y0:Cr0:Y1:cb0 8:8:8:8 little endian */
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RK_FORMAT_YVYU_420 = 0x19 << 8, /* ODD : [0:31] Y0:Cr0:Y1:cb0 8:8:8:8 little endian
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* EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */
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RK_FORMAT_VYUY_422 = 0x1a << 8, /* [0:31] Cr0:Y0:Cb0:Y1 8:8:8:8 little endian */
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RK_FORMAT_VYUY_420 = 0x1b << 8, /* ODD : [0:31] Cr0:Y0:Cb0:Y1 8:8:8:8 little endian
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* EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */
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RK_FORMAT_YUYV_422 = 0x1c << 8, /* [0:31] Y0:Cb0:Y1:cr0 8:8:8:8 little endian */
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RK_FORMAT_YUYV_420 = 0x1d << 8, /* ODD : [0:31] Y0:Cb0:Y1:cr0 8:8:8:8 little endian
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* EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */
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RK_FORMAT_UYVY_422 = 0x1e << 8, /* [0:31] Cb0:Y0:Cr0:Y1 8:8:8:8 little endian */
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RK_FORMAT_UYVY_420 = 0x1f << 8, /* ODD : [0:31] Cb0:Y0:Cr0:Y1 8:8:8:8 little endian
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* EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */
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RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8, /* 2 plane YCbCr little endian
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* plane 0: [0:9] Y
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* plane 1: 2x2 subsampled [0:19] Cb:Cr 10: 10 (default)
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* or
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* plane 1: 2x2 subsampled [0:23] Cb:Cr 16: 16 */
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RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8, /* 2 plane YCbCr little endian
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* plane 0: [0:9] Y
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* plane 1: 2x2 subsampled [0:19] Cr:Cb 10: 10 (default)
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* or
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* plane 1: 2x2 subsampled [0:23] Cr:Cb 16: 16 */
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RK_FORMAT_YCbCr_422_SP_10B = 0x22 << 8, /* 2 plane YCbCr little endian
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* plane 0: [0:9] Y
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* plane 1: 2x1 subsampled [0:19] Cb:Cr 10:10 (default)
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* or
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* plane 1: 2x1 subsampled [0:23] Cb:Cr 16: 16 */
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RK_FORMAT_YCrCb_422_SP_10B = 0x23 << 8, /* 2 plane YCbCr little endian
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* plane 0: [0:9] Y
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* plane 1: 2x1 subsampled [0:19] Cr:Cb 10:10 (default)
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* or
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* plane 1: 2x1 subsampled [0:23] Cr:Cb 16: 16 */
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/* For compatibility with misspellings */
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RK_FORMAT_YCbCr_422_10b_SP = RK_FORMAT_YCbCr_422_SP_10B << 8,
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RK_FORMAT_YCrCb_422_10b_SP = RK_FORMAT_YCrCb_422_SP_10B << 8,
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RK_FORMAT_BGR_565 = 0x24 << 8, /* [0:16] B:G:R 5:6:5 little endian */
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RK_FORMAT_BGRA_5551 = 0x25 << 8, /* [0:16] B:G:R:A 5:5:5:1 little endian */
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RK_FORMAT_BGRA_4444 = 0x26 << 8, /* [0:16] B:G:R:A 4:4:4:4 little endian */
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RK_FORMAT_ARGB_8888 = 0x28 << 8, /* [0:31] A:R:G:B 8:8:8:8 little endian */
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RK_FORMAT_XRGB_8888 = 0x29 << 8, /* [0:31] X:R:G:B 8:8:8:8 little endian */
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RK_FORMAT_ARGB_5551 = 0x2a << 8, /* [0:16] A:R:G:B 5:5:5:1 little endian */
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RK_FORMAT_ARGB_4444 = 0x2b << 8, /* [0:16] A:R:G:B 4:4:4:4 little endian */
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RK_FORMAT_ABGR_8888 = 0x2c << 8, /* [0:31] A:B:G:R 8:8:8:8 little endian */
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RK_FORMAT_XBGR_8888 = 0x2d << 8, /* [0:31] X:B:G:R 8:8:8:8 little endian */
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RK_FORMAT_ABGR_5551 = 0x2e << 8, /* [0:16] A:B:G:R 5:5:5:1 little endian */
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RK_FORMAT_ABGR_4444 = 0x2f << 8, /* [0:16] A:B:G:R 4:4:4:4 little endian */
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RK_FORMAT_RGBA2BPP = 0x30 << 8, /* [0:1] Color:Alpha 1:1 little endian */
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RK_FORMAT_UNKNOWN = 0x100 << 8,
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} RgaSURF_FORMAT;
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enum {
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yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */
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yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */
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yuv2rgb_mode2 = 0x2, /* BT.709 */
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rgb2yuv_601_full = 0x1 << 8,
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rgb2yuv_709_full = 0x2 << 8,
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yuv2yuv_601_limit_2_709_limit = 0x3 << 8,
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yuv2yuv_601_limit_2_709_full = 0x4 << 8,
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yuv2yuv_709_limit_2_601_limit = 0x5 << 8,
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yuv2yuv_709_limit_2_601_full = 0x6 << 8, //not support
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yuv2yuv_601_full_2_709_limit = 0x7 << 8,
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yuv2yuv_601_full_2_709_full = 0x8 << 8, //not support
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yuv2yuv_709_full_2_601_limit = 0x9 << 8, //not support
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yuv2yuv_709_full_2_601_full = 0xa << 8, //not support
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rgb2yuv_709_limit = 0xb << 8,
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yuv2rgb_709_full = 0xc << 8, //not support
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yuv2yuv_601_limit_2_601_full = 0xd << 8, //not support
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yuv2yuv_601_full_2_601_limit = 0xe << 8, //not support
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yuv2yuv_709_limit_2_709_full = 0xf << 8, //not support
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yuv2yuv_709_full_2_709_limit = 0x10 << 8, //not support
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full_csc_mask = 0xf00,
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};
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enum {
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RGA3_SCHEDULER_CORE0 = 1 << 0,
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RGA3_SCHEDULER_CORE1 = 1 << 1,
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RGA2_SCHEDULER_CORE0 = 1 << 2,
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};
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/* RGA3 rd_mode */
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enum
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{
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raster_mode = 0x1 << 0,
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fbc_mode = 0x1 << 1,
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tile_mode = 0x1 << 2,
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /*_RK29_IPP_DRIVER_H_*/
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